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Yi-Chip · Frequency Synthesis & Clocks (PLL)

SYF4000

3.6-4.6GHz Integer-N PLL

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Specifications & Features

  • 3.6-4.6GHz Integer-N PLL



Typical Applications

  • Wireless infrastructure (MC-GSM, 5G)

  • Satellite/VSAT

  • Test Equipment / Instrumentation

  • Clock generation

  • Aerospace/Defense


Selection Notes

SYF4000 is a low-power, ultralow-noise integer-N phase-locked loop IC that generates integer multiples of the reference frequency within 3.6GHz-4.6GHz. It includes a fully integrated voltage-controlled oscillator and selectable dividers. SYF4000 can switch between a conventional PFD architecture and a subsampling architecture for improved performance. In subsampling mode, it provides a normalized noise floor of -235.5dBc/Hz and can operate at a phase-detector frequency of 400MHz.

The device is available in a plastic QFN 56 package, with an operating temperature range of -45℃ to +85℃.

♦ Low power consumption, multi-device synchronization, fast lock and low phase noise;

♦ Programmable output division by 2, 4, 8, 16, 32 and 64;

♦Reference frequency range: 10MHz-400MHz;

♦ Reference spurs: -60dBc;

♦ Supply voltages: 1.0V & 1.8V;

♦Power consumption: 0.065W (typical);

♦ Output frequency range: 3.6-4.6GHz;

♦ Integrated rms jitter: 79fs (1kHz-100MHz);

♦Normalized phase noise floor: -235.5dBc/Hz;

♦ Phase noise: -121.3dBc@1MHz (4GHz output frequency);

♦ Operating temperature: -40 to 85℃;

♦Plastic QFN 56 package;



Public information is intended for preliminary product selection. Check specifications against the specific frequency, bandwidth, configuration, package, and interface conditions. For detailed technical documentation, specify the model and system requirements.

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